Staff Layout Engineer
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Staff Layout Engineer
IC Layout
IC Layout
Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout Schedule time-line & layout floor-planning Complete quality layout and verification within planned schedule (without supervision for experienced engineer) Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team
Skill Set (Mem)
- Strong experience in memory layout design and physical verifications, including LVS, DRC, ERC, Antenna, and Electro Migration in CMOS processes.
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Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools.
Good experience in Floor-planning, hierarchy layout and chip integration.
Experience in memory compiler will be a plus.
Knowledge of Script Programming and SKILL Programming would be a plus.
Able to lead or train a team of junior engineers
Good knowledge of memory layout topology.
Ability to lead new technology reviews to compile documentation of layout methodology, layout flow and guidelines.
Self-reliant, with the ability to work independently as well as in a team.
Re-location
Must be available to re-locate to Singapore immediately.
Not included in the source posting: what you'll do, benefits.
Who can apply
The employer didn't state any visa, work authorization, citizenship or clearance requirements in this posting. Confirm with the employer before applying.
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