Sr. Staff Validation Engineer
About Marvell
Your Team, Your Impact
What You Can Expect
- Execute silicon bring-up and validation test plans for ASIC/SoC products with CXL 3.x, HBM, DDR, PCIe, and high-speed SerDes interfaces.
- Set up and maintain lab test environments, including boards, power supplies, clocks, resets, and cabling, to ensure stable and repeatable measurements.
- Operate lab equipment such as oscilloscopes, logic analyzers, protocol analyzers (PCIe/CXL), pattern generators, BERTs, power supplies, and environmental chambers.
- Develop and use scripts (Python, TCL, shell, MATLAB or similar) for lab automation and data collection/analysis.
- Run experiments to characterize link and memory behavior (e.g., throughput, latency, BER, margins, power) and summarize results.
- Assist in debugging issues across silicon, firmware, board, and test setup; capture logs, traces, and measurement data for senior engineers.
- Document test procedures, lab setups, and results; provide clear, concise updates to the validation lead and cross-functional teams.
- Contribute feedback to improve test plans, lab infrastructure, and validation processes.
What We're Looking For
- Bachelor's degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience. OR Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience
- 3+ years of experience in silicon or system validation, hardware test, or related lab-based roles.
- Working knowledge of high-speed interfaces and memory subsystems (e.g., PCIe, CXL, DDR, HBM, SerDes concepts).
- Hands-on experience with lab instruments (oscilloscope, logic analyzer, protocol analyzer, power supplies, etc.).
- Experience with at least one scripting language used in lab environments (e.g., Python, TCL, shell).
- Strong problem-solving skills and attention to detail in executing tests and recording results.
Preferred Qualifications
- Experience with validation or test of high-speed digital interfaces (PCIe, CXL, DDR, HBM or SerDes-based links).
- Exposure to first silicon bring-up or early hardware prototyping.
- Familiarity with version control and issue tracking tools used in engineering
Expected Base Pay Range (USD)
127,630 - 191,200, $ per annum The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.
Additional Compensation and Benefit Elements
Interview Integrity
Not included in the source posting: what you'll do.
Skills
Who can apply
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