Sr Principal Design Engineer
About the role
Candidate must have a thorough understanding of the following
- Mixed-signal circuit design fundamentals
- Mixed-signal circuit design and verification flows
- Cadence analog design environment
- Basic signal processing concepts
Familiarity with the following items is a plus
- Serial link design techniques
- Data converter (ADCs and/or DACs) and/or clock synthesis and recovery (PLLs, DLLs, CDRs) techniques
- MATLAB or C to facilitate architecture development
- Hardware description languages such as SystemVerilog or VerilogA for functional model development
- Scripting languages such as Perl or Python for automation
- Silicon validation testing knowledge and experience
Other requirements
- Excellent verbal and written communication skills
- Ph.D. EE degree with 5+ years or MS EE. degree with 7+ years of mixed signal design industry experience in advanced process technologies
The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. Be proud and passionate about the work you do. Together, our One Cadence -- One Team culture drives our success.
Not included in the source posting: about the role, benefits.
Skills
Who can apply
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