Soc Engineer (synthesis/timing)
About the role
Responsibilities and Duties
- Synthesis
- LEC
- LDRC
- GCA
- STA
- PTPX
Responsible for the development and implementation of System Design Solutions using Synopsys EDA tools and IP to solve customer problems as part of a service project team. Contributes to both turnkey projects and as a trusted advisor to customer design. Develop innovative solutions to problems with little guidance and implement them independently. Set task-level goals and consistently meet schedules. Works with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tool and IP solutions.
Qualifications
- 6-12 years of related experience.
- Good of ASIC/SOC design, synthesis, timing closure.
- Familiar with Synthesis, LEC, STA flow.
- It's a plus if you have experience in low-power, high-performance design, advanced nodes under 12nm.
- Knowledge of RTL, DFT, LDRC, GCA, VCLP, PTPX, IREM is advantageous.
- Familiar with scripting languages, such as TCL, Perl, Python.
- Good English/communication skills and willingness to work with customer.
- BS or MS with an EE or related major
Not included in the source posting: about the role, benefits.
Skills
Who can apply
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