Package Design Engineer

Responsible for all aspects of advanced semiconductor package design for mixed signal, RF, microwave, and mmWave products, including package architecture development, die-package codesign, package layout, design rule compliance, manufacturability and reliability optimization, and technical documentation.

The successful candidate will work closely with BL partners, SoC designers, package engineers, project managers, simulation specialists, assembly sites including OSATs and substrate suppliers to develop package solutions that meet electrical, thermal, mechanical, reliability, manufacturability, and cost objectives.

Key Responsibilities

• Responsible for all aspects of package design from concept through best in class solution with optimal cost, manufacturability, performance and reliability.
• Utilize various industry standard die / package co-design and layout tools for design.
• Participate in die/package/PCB codesign activities, supporting critical signal paths, package architecture, floorplanning, bump maps, stackups, and routing implementation.
• Design and optimize package structures for RF and mmWave applications, including controlled-impedance routing, grounding, shielding, and signal-launch structures.
• Collaborate with simulation engineers to evaluate electrical performance, SI/PI, EM behavior, and implement design improvements.
• Support package design reviews, manufacturability assessments, design-rule compliance, and release documentation.
• Partner with assembly sites, OSATs, substrate suppliers, and cross-functional teams to deliver robust, manufacturable package solutions.
• Provide technical guidance on package architecture, substrate technologies, assembly processes, and RF package implementation.

• Bachelor's or Master's degree in Electrical, Mechanical, Materials Engineering, or equivalent.
• Technical experience in the following areas:
• Five plus years direct experience designing flip chip and wire-bond substrate-based and WLCSP/FOWLP semiconductor packages.
• Expert proficiency with Cadence Allegro Package Designer (APD) and AutoCAD required.
• Experience with die-package-PCB codesign methodologies desired.
• Knowledge of Power Integrity and Signal Integrity (PISI) and high-speed signal routing, differential pair implementation, return-path management, and impedance-controlled interconnect design a plus.
• Strong understanding of substrate technologies including design rules as well as Geometric Dimensioning and Tolerancing.
• Experience with or extensive exposure to primarily analog SoC design prefrred.

• Effective written, verbal and presentation communication skills.
• Strong technical leadership and problem-solving skills.
• Demonstrated ownership and accountability for technical deliverables.
• Self-motivated and capable of driving technical execution with minimal supervision.
• Strong collaboration and teamwork skills in a global engineering environment.

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