Hybrid SoC Verification Engineer II (SystemVerilog/UVM)
Silicon Labs Careers
SingaporePosted Discovered via the company's careers siteMatch locked
HybridFull-timeEngineering Jobs
About the role
Silicon Labs seeks an experienced SoC verification engineer to join our IoT Digital Design team in Singapore. You will develop and execute verification plans for Wireless MCU SoCs, build SystemVerilog/UVM testbenches, and drive coverage closure across RTL and emulation environments. You will collaborate with RTL, architecture, firmware, and validation teams, mentoring junior engineers while advanc
Not included in the source posting: about the role, what you'll do, qualifications, benefits.
Skills
soc
Who can apply
The employer didn't state any visa, work authorization, citizenship or clearance requirements in this posting. Confirm with the employer before applying.
Read automatically from the employer's posting text. Always confirm with the employer — requirements can change after a job is published.