Design Verification Engineer
HCLTech
OthersPosted Discovered via the company's careers siteMatch locked
Full-time2+ years exp
Job Summary
We are seeking skilled Design Verification (DV) Engineers to validate complex ASIC/SoC/IP designs. The role involves developing scalable verification environments, creating test plans, and ensuring functional correctness through advanced verification methodologies such as UVM.
You will work closely with design, architecture, and physical design teams to deliver first-time-right silicon.
Key Responsibilities
- Develop
directed and constrained-random testcases
- Debug failures and root-cause issues across RTL, testbench, and tools
- RTL as well as Gate level simulations
- Automate regression flows and improve verification productivity
Technical Skills
- Good knowledge of
SystemVerilog
- Hands-on experience with
UVM (Universal Verification Methodology)
- Experience with
EDA tools
(e.g., VCS, Verdi)
- Experience in
debugging RTL and gate level simulation issues
- Good knowledge of PCIe
2–5 years Programming/Scripting
- Proficiency in
Python/Perl/Shell scripting
for automation
Education
- B.Tech / M.Tech in Electronics / Electrical / Computer Engineering or equivalent
Other Requirements
- Strong analytical and debugging skills
- Good communication and cross-functional collaboration
Not included in the source posting: about the role, benefits.
Skills
perlpythonsoc
Who can apply
The employer didn't state any visa, work authorization, citizenship or clearance requirements in this posting. Confirm with the employer before applying.
Read automatically from the employer's posting text. Always confirm with the employer — requirements can change after a job is published.