VLSI Design Verification Internship
About the role
Who We Are
Job Description
Responsibilities
- Develop SystemVerilog and UVM testbench components, including models, monitors, scoreboards, and checkers
- Write constrained-random tests
- Develop and analyze functional coverage to identify verification gaps
- Debug regression failures and help identify, log, and resolve logic bugs
- Work directly with ASIC designers and architects
- Use scripting, automation, and AI-assisted tools to improve the verification process
Requirements
- Pursuing a bachelor's or master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
- Coursework in digital design and computer architecture
- Experience with object-oriented programming
- Strong analytical and problem-solving skills
- Clear written and verbal communication skills
- Willingness to ask questions, explain your reasoning, and participate in technical discussions
Preferred skills
- Experience with a hardware description language such as Verilog, SystemVerilog, or VHDL
- Experience with Python, Perl, Tcl, or another scripting language
- Experience working in Linux development environments
- Academic, research, or personal projects involving digital hardware
- Experience working as part of a distributed team
Accessibility
HPE is committed to creating an inclusive and accessible workplace and encourages applications from all qualified individuals, including those with disabilities. If you believe you require accommodation during any stage of the application or interview process, please submit your request by completing our secure form linked here .
Note: This option is reserved for applicants needing assistance/reasonable accommodation related to a disability.
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Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.
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Not included in the source posting: benefits.
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