Sr / DFT Engineer ( IP / ASIC / SoC)
AUREXIS TECH PTE. LTD.
SingaporePosted about 1 month agoDiscoveredMatch locked
Full-timeEngineering Jobs
About the role
Main Responsibilities Work closely with design teams and make sure DFT structures are correctly implemented Responsible for verifying DFT schemes on IPs in ASIC and FPGA products Responsible for block level and SoC level ATPG and verification with DFT rule check and debug for various testing modes Responsible for memory tests (MBIST, BISR), IEEE1149.1 JTAG and IEEE1687 iJTAG Responsible to develop
Not included in the source posting: about the role, what you'll do, qualifications, benefits.
Skills
soc
Who can apply
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