Senior Technical Architect
HCLTech
King, Washington, United StatesPosted about 2 months agoDiscoveredMatch locked
Full-time
Job Summary
Physical Design Engineer, Performs block-level implementation and optimization activities to achieve timing, power, area, and routing goals.
Key Responsibilities
- Floorplanning and macro placement
- Placement optimization
- Clock Tree Synthesis (CTS)
- Routing and ECO implementation
- Timing closure support
- Congestion and utilization optimization
- DFM and signoff fixes
- Support tape-out activities
Skill Requirements
- ICC2/Fusion Compiler/Innovus expertise
- Understanding of ASIC implementation flow
- Timing analysis fundamentals
- CTS and routing concepts
- TCL, Perl, Python scripting
- LEF/DEF, Liberty, Verilog knowledge
- Basic understanding of IR/EM and Physical Verification
Not included in the source posting: about the role, benefits.
Skills
perlpython
Who can apply
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