Senior SOC Design Engineer - Networking Group

• You are encouraged to understand all features of a given project and define project milestones based on internal roadmaps, assign them and track them through agile framework

• Define and develop system-level methodologies, tools, and IPs to build subsytems in an efficient and scalable manner.

• Work with SOC Assembly team and drive cross-functional teams towards SOC milestone execution.

• Be responsible for integrating all the pieces for a given defined project milestone and deliver the model to relevant teams for further verification at cluster/sub-system/SOC/emulation levels.

• BS (or equivalent experience) / MS with 3+ years of practical semiconductor design and architecture experience building complex SoC's.

• Must have firsthand experience & solid understanding of all phases of SOC development in multiple ASIC projects including ASIC architecture, Micro-Architecture, RTL design, verification, timing closure & Physical design.

• Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.).

• C/C++ programming or python or any other industry-standard scripting language experience desirable.

• Experience working with software teams to tightly define the HW/SW interface including control/status registers, interrupt and error handling.

• Hands on experience in successful tape outs of multiple sophisticated, high-volume SoCs in advanced process nodes.

• Exposure to various Chip Design Functions to be able to collaborate and tackle sophisticated cross functional problems.

• Excellent verbal and written communication skills to interact with cross functional teams to build consensus.

• Experience in synthesis, physical design and DFT is a plus.

• Experience in RTL Build and Design Automation is a plus.

• Chip lead type of technical leadership experience on delivering complex SOCs for enterprise and/or HPC applications.

• Experience in RTL coding and debug, as well as performance/power/area analysis and trade-offs

• Experience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area.

• Prior experience of smartNIC and/or high-speed interconnects.

• Strong coding skills in Perl, Python, or other industry-standard scripting languages.

Known throughout the technology industry as a top employer, NVIDIA delivers highly competitive salaries and a thorough benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/

NVIDIA is committed to encouraging a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

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