Senior Engineer (Level 1)
Arrow
IndiaPosted about 22 hours agoDiscoveredMatch locked
Full Time4+ years expEngineering Jobs
About the role
Position: Senior Engineer (Level 1) Job Description: Roles and Responsibilities: · 4 to 8 years of experience in SOC/IP/block level functional verification using System Verilog/UVM. · Strong knowledge of UVM, advance UVM,System Verilog . · Must have worked on development of testplan, testbench components, verification environment, interface agents, Scoreboard in UVM. Understanding of complete func
Not included in the source posting: about the role, what you'll do, qualifications, benefits.
Skills
soc
Who can apply
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