Senior DFT Engineer: IP/ASIC/SoC | Impactful Debug
AUREXIS TECH PTE. LTD.
SingaporePosted about 1 month agoDiscoveredMatch locked
Full-timeEngineering Jobs
About the role
AUREXIS TECH PTE. LTD. is seeking an engineer to collaborate with design teams to implement DFT structures and verify DFT schemes across ASIC and FPGA IPs. The role covers block and SoC level ATPG verification with DF T rule checks, and debugging across multiple test modes. The candidate will contribute to MBIST/BISR, IEEE1149.1 JTAG, and IEEE1687 iJTAG testing, while developing firmware-driven te
Not included in the source posting: about the role, what you'll do, qualifications, benefits.
Skills
soc
Who can apply
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