Senior Design Lead
HCLTech
Bucuresti, RomaniaPosted about 2 months agoDiscoveredMatch locked
Full-time
JD
Candidate will be responsible for high performance controller (PCIe gen 6/7, LPDDR 5/6, Ethernet) IP verification.
- Extract verification requirements from spec
- Experience in architecting and writing Testbench from scratch or adding UVM components to an existing testbench.
- Solid background in UVM/ System Verilog
- Usage of protocol VIPs (PCIe, Ethernet, LPDDR, AMBA). Ability to debug VIP
- Ability to define & write new tests
- SVA - need to know how to write complex assertions checkers to validate functionality.
- experience with writing coverage and stimulus to get the coverage for sign off.
- Working as part of a Team with good debug skills.
- Good communication skill to communicate bug/issues effectively
- Able to work independently
Key Responsibilities
Candidate will be responsible for high performance controller (PCIe gen 6/7, LPDDR 5/6, Ethernet) IP verification.
Not included in the source posting: about the role, qualifications, benefits.
Who can apply
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