Senior Design Lead - Design Validation

Good understanding of ASIC/SoC life cycle Has participated in multiple ASIC/SoC verification till tapeout stage Experience writing ASIC/SoC testplans "1.Experience in ASIC/SoC Testbench definition 2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM)." "1.Expertise & hands-on experience in OVM/UVM methodologies using SV 2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans." "1. Experience in developing TB components for SOC with C, SV " "1. Experience in developing TB components, including functional coverage implementation and assertion coding

1. Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.

3.Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.

1. Experince in SOC C based tests coding & debugging"

"Experience in Gate level simulation & netlist debugging " "Exeprince in regression failure analayiss Functioncal and Code Coverage closure" Experience in Perl/Shell scripting