Senior Design Lead - Design Validation

Experience 5 to 10 years. Define ASIC/SoC verification strategy Full chip testplan development Full chip TB Architecture definition UVM based testbench development SV functional coverage, Assertions coding C based TB development Test case development, coding, execution, bug analysis Gate Level Simulation Regressions, coverage analysis participate in verification closure.

Good understanding of ASIC/SoC life cycle Has participated in multiple ASIC/SoC verification till tape out stage Experience writing ASIC/SoC test plans Experience in ASIC/SoC Testbench definition Experience to Build and maintain reusable block-level and sub-system testbenches using System Verilog and the Universal Verification Methodology (UVM)." Expertise & hands-on experience in OVM/UVM methodologies using SV Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans." Experience in developing TB components for SOC with C, SV Experience in developing TB components, including functional coverage implementation and assertion coding Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic. Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues. Experience in SOC C based tests coding & debugging"

Digital Logic: Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts. EDA Tools: Familiarity with industry-standard simulation and debugging tools (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verdi).

Protocols: Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C,PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE)." Scripting: Basic comfort working in a Linux environment and using scripting languages like Python, Tcl, or Perl for automation.