
Senior ASIC Verification Engineer, Lund
About the role
The ASIC Verification Team
About you
We are looking for a Bachelor's or Master's degree in Computer Science, Electrical/Computer Engineering, or a related field. You should have experience from at least a couple of projects developing sophisticated compute subsystems or SoCs, ranging from specification and modelling phase to tape out.
You will need:
- Solid understanding of digital hardware Verilog HDL and Verification strategies including, SystemVerilog, UVM and Hardware/Firmware co-verification.
- Experience in complex SoC architecture and development including multi-clock domain designs, AXI/APB protocols, multi-power domains, and reset architectures.
- Experience with Python, Tcl, or other scripting language.
- Experience verifying SoC projects or systems including embedded microprocessors.
Bonus points for:
- End to end formal verification and formal property verification
- Clock domain crossing verification and connectivity checking
- Power aware verification
- Transaction Level Modeling (TLM) and SystemC
You enjoy sharing your knowledge and ideas with co-workers. You want to be part of a competent and creative team that loves to solve problems together, and we are sure that we are that team!
Your role
What Axis has to offer
Ready to act?
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Who can apply
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