Senior Analog/Mixed-Signal Circuit Design Engineer (PLL/VCO)
Brightecs Innovation Pte Ltd
SingaporePosted 30 days agoDiscoveredMatch locked
Full-timeEngineering Jobs
About the role
Brightecs Innovation Pte. Ltd. (BIP) in Singapore seeks a senior RFIC/PLL engineer to lead advanced CMOS PLL architecture, layout, and verification. You will drive architecture choices, calibrations, and testing to achieve sub-100 fs jitter and wide tuning ranges with robust PVT behavior. The role emphasizes device-level design, layout leadership, and chip verification, leveraging LabView/Python/M
Not included in the source posting: about the role, what you'll do, qualifications, benefits.
Skills
matlabpython
Who can apply
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