Product Failure Analysis Engineer - SCAN Design for Test
Job Description
Key Responsibilities
- Lead Failure Analysis: Utilize state-of-the-art lab equipment - including FIB tools, probe tools, and automated systems - to isolate microscopic silicon circuit failures and identify root causes with precision and speed.
- Drive Cross-Functional Collaboration: Partner with test and validation engineers, circuit designers, wafer fabrication process engineers, and high-volume manufacturing teams to resolve quality issues, develop temporary mitigations, and implement permanent remedies.
- Advance Debug Technologies: Develop new debug tools, methodologies, and technologies that push the boundaries of silicon debug, contributing to breakthrough innovations in semiconductor manufacturing.
- Ensure Design for Debug: Evaluate and resolve component engineering and physical design issues, ensuring products incorporate the necessary design-for-debug features to enable deep silicon isolation capabilities.
- Support Continuous Improvement: Provide expert input on failure analysis investigation areas and design process improvements, ensuring products consistently perform to specification.
As a Successful Candidate, You Will Bring:
- A collaborative spirit - you thrive in cross-functional environments and build strong relationships across teams.
- Intellectual curiosity - you love diving deep into complex problems and aren't satisfied until you've found the root cause.
- Resilience and adaptability - you stay focused and effective even when working on the most challenging, ambiguous problems.
- Clear communication - you can translate highly technical findings into clear, actionable insights for diverse audiences.
- Ownership mentality - you take pride in your work and hold yourself accountable for delivering results.
- Innovation mindset - you're always looking for better ways to do things and aren't afraid to challenge the status quo.
Ideal Background
- 6+ years of semiconductor industry experience in Product Engineering, Failure Analysis, Silicon Debug, DFT, Yield Engineering, or Post-Silicon Validation.
- Deep expertise in DFT architectures, ATPG, scan diagnosis, and fault modeling.
- Experience debugging complex silicon issues on leading-edge technology nodes.
- Strong understanding of failure analysis workflows and physical debug techniques.
- Demonstrated success driving cross-functional investigations from problem identification through corrective action.
- Experience developing automation and debug methodologies that improve diagnosis accuracy and turnaround time.
- Passion for advancing semiconductor technology and contributing to the successful deployment of Intel Foundry 18A products.
If you're passionate about silicon engineering and want to work on technology that matters, we'd love to hear from you.
Apply today
Minimum Qualifications
- Bachelor's degree in electrical engineering, computer engineering, or a related STEM discipline with 6+ years of hands-on experience, OR master's degree with 4+ years, OR PhD with 2+ years.
- Hands - on experience with the following: • Expertise in Design for Test (DFT) tools and techniques, SCAN ATPG methodology, and Scan Chain Diagnosis.
- In fault isolation techniques including ATPG pattern generation, fault modeling (stuck-at, transition, path delay, bridging), and Scan architecture (SSN).
- Experience with Siemens Tessent, Synopsys TestMAX/TetraMAX, Verdi, DVE, simulation and diagnosis tools
- Experience developing debug automation and analysis tools using Python, Perl, or TCL
Preferred Qualifications:
- 6+ years of experience: • JTAG and validation/debug research methodologies.
- Developing innovative debug tools and methodologies in a research-driven environment.
- In foundry, fabless semiconductor, or high-volume manufacturing environments supporting customer product bring-up, yield ramp, or production qualification.
Job Type
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Primary Location
Posting Statement
Benefits
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
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