Process Engineer – Die to Wafer Hybrid Bonding

Salary: $147,000.00 - $202,500.00 Location: Santa Clara,CA You'll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible - while learning every day in a supportive leading global company. Visit our Careers website to learn more.

At Applied Materials, we care about the health and wellbeing of our employees. We're committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits .

As a Process Engineer, you'll play a crucial role in designing and optimizing manufacturing processes for display and semiconductor manufacturing technologies. You will collect and analyze data, perform hardware characterization, and troubleshoot engineering issues. You'll also measure film properties, generate technical documentation, and engage with customers to resolve concerns. Process Engineers collaborate with vendors and suppliers, and become familiar with implementing new technologies and products. You will experiment, learn, and collaborate with some of the brightest minds in the semiconductor and display industries, partnering with our globally recognized R&D teams on state-of-the-art research and development projects.

Join the Photonics Platforms Business Group at Applied Materials' Santa Clara headquarters, where you will work with a cross-functional research team to develop cutting-edge 2.5D/3D advanced packaging technologies.

We are seeking hands on Process Engineers to drive die to wafer (D2W) hybrid bonding R&D. This role focuses on hybrid bonding process development, pathfinding, technology de risking, and advanced packaging integration exploration. The role provides on the job training and hands on experience with state of the art equipment, including the industry's first fully integrated die to wafer hybrid bonding system.

Key Responsibilities

• Develop die to wafer hybrid bonding processes, including (but not limited to):

• Surface preparation and plasma activation
• High accuracy die placement and alignment
• Post bond characterization and process evaluation

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• Dicing and die preparation
• Die thinning
• Inter die gap fill and planarization
• Design and execute DOE driven experiments to understand process limits, sensitivities, and trade offs.
• Own process optimization, perform failure analysis and characterization, and drive continuous engineering improvement.

• Ph.D. or M. S. in Materials Science, Electrical Engineering, Applied Physics, or a related STEM discipline.

• Die to wafer or wafer to wafer hybrid bonding
• Thin die handling and alignment critical processes
• Micro-LED or CPO experience
• Heterogeneous integration such as III-V to Si, novel materials to Si 2.5D/3D integration
• Direct process engineer experience on mainstream semiconductor equipment (plasma, wet clean, overlay/alignment, etc.)

• Bond interface physics
• Alignment and overlay fundamentals
• Mechanical behavior of thin and fragile dies
• Proficiency in statistical analysis and process control (e.g., DOE, SPC, JMP).
• Self starter with strong problem solving skills; able to work both independently and collaboratively with minimal supervision.
• Strong communication and interpersonal skills, with the ability to collaborate effectively across multidisciplinary teams.