Principal Hardware Engineer - 3rd Party IP Engineer

In this role, you will work in parallel with a team of 3rd party IP engineers responsible for bringing in all subcontracted IP under the Marvell IP umbrella. This is a dynamic and challenging role, and, in this position, you will engage all parts of Marvell.

Looking for a talented 3rd party IP integration engineer to assist Marvell in offering DDR/LPDDR/GDDR/HBM/eMMC memory interface cores to our clients. Become part of a team creating leading-edge designs for the latest applications in artificial intelligence, hyper-scaler, communications, and storage.

As a 3rd party core integrator, you will be involved in all stages of SoC development including defining core requirements, validating IP developer competence, overseeing core development, technology compliance, core integration, test compliance and silicon validation.

in this role you will:

• Assist sales in winning bids by working with leading edge IP providers to meet customer requirements.
• Manage 3rd party developers in completing core designs and providing required design rules.
• Advise the Marvell design center on core integration into custom silicon designs and hold joint reviews with the design center and 3rd party IP provider. Responsibilities will also include developing statements of work, leading provider progress reviews, using 3rd party developer problem reporting tools to drive to problem resolution.
• Assist with 8D follow-through for significant supplier issues.

What We're Looking For

• Bachelor's degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience. OR Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.
• Proficient in understanding of DDR type interfaces (DDR, LPDDR, GDDR, HBM, eMMC), including the challenges associated with SoC PHY integration, timing analysis, packaging, and multi-chip integrated packaging
• Proficient in project management tasks required to manage 3rd party developers
• Broad-based exposure to ASIC design flows required for releasing a chip to fabrication including logic synthesis, physical design, timing, DRC/LVS, Formal verification and electrical checking
• Good understanding of Design-For-Test concepts including DFT logic insertion, test generation, scan and embedded core testing
• Good communication and customer management skills
• Post-silicon validation at customer sites will require a limited degree of travel.

Expected Base Pay Range (USD)

0 - 0, $ per annum The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.