Intern: Application Engineering - Digital Verification & Simulation/VIP

to work with us in Belo Horizonte, Brazil.

As an Intern: Application Engineering - Digital Verification & Simulation (VIP), you will be trained to become an expert in Digital Verification & Simulation methodologies in the System Verification Group - Technical Field Operations (TFO-SVG) in Belo Horizonte. The TFO-SVG group works with Xcelium, Palladium, Protium, Jasper, VIPs, Perspec, and other Cadence Digital Functional Verification tools.

The application engineers provide technical support, enabling customers to effectively deploy our industry-leading technology, focused on RTL-level verification products. You will be in a Digital Verification & Simulation focused team working with our Verification IP Solutions, complimentary tools, and its customers to understand their needs and provide guidance on the best technologies and methodologies to enable their success, coming up with innovative solutions to address the industry's most challenging problems.

Job Description:

• Activities focused on the Functional Verification field as mentioned above, mentored by experienced colleagues, and reporting to higher management.
• Provide technical support to customers and field personnel in RTL verification solutions focused on the Cadence Verification IP solutions and supporting technologies.
• Conduct root cause analysis and provide resolution to customer technical issues.
• Help to develop and run test cases to verify problems, create workarounds when possible, test and deliver R&D fixes.
• Close collaboration with R&D on issues using established protocols.
• Author application notes and help provide feedback on documentation.
• Help use scripting languages like TCL and Python for flow development, automation and enhancing design methodologies.

• Ongoing bachelor's in Electrical Engineering, Computer Engineering, Electronics Engineering, Control and Automation Engineering, Systems Engineering, Computer Science, Information Systems, Computational Mathematics, or related areas.
• Graduating in mid 2027
• Good problem-solving skills.
• Strong inter-personal and communication skills.
• A strong interest in learning the technical topics mentioned above.

• Exposure to RTL (Verilog or VHDL) is a plus.
• Experience in scripting languages such as TCL and Python is a plus.

• Employment category: Internship.
• Employment term: 20 hours/week.
• Competitive benefits.
• Av. do Contorno 5800, Savassi, Belo Horizonte, Minas Gerais