Fellow, Integrated Solutions & Ecosystem Architecture
HP
Palo Alto, California, United States of America; Spring, Texas, United States of AmericaPosted 5 days agoDiscoveredMatch locked
Full time
About the role
Fellow, Integrated Solutions & Ecosystem Architecture
Why this role is critical to HP
The next generation of personal computing will be defined across company boundaries. Silicon, operating systems, AI platforms, memory, security, cloud services, firmware and device experiences increasingly evolve on independent roadmaps, yet must operate as one integrated system in the products customers use.
HP is seeking a Technical Fellow to serve as the senior technical leader for partner architecture and ecosystem engineering across Personal Systems. This leader will work directly with HP's most strategic technology partners and with engineering teams across HP to turn separate technology roadmaps into integrated, multi-generation product architectures.
The role will shape joint technical direction, establish the architectural interfaces and commitments required across organizations, identify where HP should build, integrate or co-engineer, and drive the technology workstreams needed to convert capabilities into differentiated products.
This is a critical hands-on senior technical leadership role accountable for architecture, roadmap convergence, technical decisions and co-engineering outcomes across company boundaries.
Key responsibilities
•
Lead HP’s technical architecture engagement with strategic ecosystem partners
across silicon, operating systems, AI platforms, memory and storage, cloud, device technologies and system software.
•
Create integrated multi-generation technology roadmaps
connecting partner capabilities, HP engineering priorities and future product requirements; identify dependencies, gaps and critical decisions early enough to influence both HP and partner roadmaps.
•
Define HP’s technical asks to partners.
Translate customer needs, system requirements and architectural direction into specific partner capabilities, interfaces, engineering commitments and product intercepts.
•
Drive common architecture and leverage across the Personal Systems portfolio.
Establish where platforms, interfaces, software components, firmware capabilities, validation methods and system technologies should be common and reusable, while preserving meaningful product differentiation.
•
Lead architecture across organizational boundaries inside HP.
Connect device engineering with HP-wide AI, software, security, manageability, services and experience teams so independently developed capabilities come together as complete system solutions.
•
Drive joint technology workstreams from concept through engineering commitment.
Establish clear technical outcomes, owners, dependencies, milestones and acceptance criteria with internal teams and external partners; ensure promising technologies progress beyond demonstrations into product-ready capabilities.
•
Shape HP’s architecture for next-generation AI and agentic computing.
Drive system-level decisions spanning CPU/GPU/NPU execution, memory, power, thermals, firmware, operating systems, AI runtimes, security, manageability and device-edge-cloud integration.
•
Resolve complex cross-company architecture tradeoffs.
Provide senior technical judgment where performance, cost, power, memory, security, roadmap timing, product requirements and independently managed partner priorities conflict.
•
Represent HP as a senior technical counterpart with industry leaders.
Engage partner CTOs, Fellows, architects and engineering executives to influence technology direction, establish joint priorities and secure engineering commitments.
•
Build HP’s partner-architecture capability and technical bench.
Lead and mentor a small team of senior architects and technical leaders, develop future technical talent and strengthen HP's ability to operate credibly at the highest levels of the industry.
What success looks like
- HP influences partner roadmaps earlier. Important HP requirements appear in partner architectures, engineering plans and future technology releases rather than being addressed after roadmaps are fixed.
- Partner engagement produces engineering outcomes. Joint work results in committed resources, interfaces, technology deliverables, reference implementations and capabilities that reach HP products.
- Architecture converges earlier across HP and its partners. Dependencies and technical tradeoffs are resolved before they become late product issues, reducing duplicated work, redesign and schedule risk.
- HP gains greater leverage from common architecture. Reusable system capabilities, interfaces and validation approaches are adopted across multiple product lines and generations.
- Emerging technology translates into product differentiation. New silicon, software, AI and ecosystem capabilities move systematically from evaluation to co-engineering to product adoption.
- HP becomes a stronger technical voice in the ecosystem. Strategic partners increasingly engage HP as a technology co-designer whose requirements and architecture help shape future platforms.
- HP builds deeper technical leadership. Senior architecture expertise grows inside the company, with a stronger bench and succession pipeline for critical technical roles.
Required experience and capabilities
- Exceptional record of technical leadership across complex, large-scale computing platforms or product ecosystems.
- Deep systems architecture expertise spanning several of the following: silicon, operating systems, firmware, system software, AI/ML systems, memory, security, manageability, cloud/edge computing and hardware platforms.
- Demonstrated experience shaping multi-generation technology roadmaps with major external technology partners.
- Proven ability to turn emerging technologies and architectural concepts into shipping platforms, products or broadly deployed capabilities.
- Experience negotiating consequential technical tradeoffs across companies and organizations with different priorities, roadmaps and business models.
- Strong understanding of system-level performance and the interactions among compute, memory, power, thermals, firmware, software and workload behavior.
- Executive presence and technical credibility to work effectively with CTOs, Fellows, senior engineering executives and business leaders.
- Ability to operate effectively with incomplete information, rapidly changing technology and complex organizational dependencies while still driving decisions and execution.
- Demonstrated ability to lead through influence across organizations where direct reporting authority does not exist.
- Track record of attracting, mentoring and developing exceptional senior technical talent.
Preferred experience
- Senior architecture leadership in personal computing, semiconductor, operating-system, AI-platform, cloud/edge or large-scale device organizations.
- Experience working directly with major silicon, operating-system, AI, memory, cloud and device-ecosystem companies.
- Experience spanning both technology creation and productization - not solely research, standards or product execution.
- Experience with multi-platform architectures involving multiple silicon vendors, operating environments and product categories.
- Experience developing joint reference architectures, co-engineering programs, industry standards or major partner-dependent technology initiatives.
- Advanced degree in Computer Science, Computer Engineering, Electrical Engineering or a related discipline, or equivalent depth of industry experience.
The pay range for this role is $350,000
to
$450,000
USD annually with additional opportunities for pay in the form of bonus and/or equity (applies to United States of America candidates only). Pay varies by work location, job-related knowledge, skills, and experience.
Benefits:
HP offers a comprehensive benefits package for this position, including:
- Health insurance
- Dental insurance
- Vision insurance
- Long term/short term disability insurance
- Employee assistance program
- Flexible spending account
- Life insurance
- Generous time off policies, including;
- 4-12 weeks fully paid parental leave based on tenure
- 11 paid holidays
- Additional flexible paid vacation and sick leave ( US benefits overview )
The compensation and benefits information is accurate as of the date of this posting. The Company reserves the right to modify this information at any time, with or without notice, subject to applicable law.
Job -
Engineering
Schedule -
Full time
Shift -
No shift premium (United States of America)
Equal Opportunity Employer (EEO) -
HP, Inc. provides equal employment opportunity to all employees and prospective employees, without regard to race, color, religion, sex, national origin, ancestry, citizenship, sexual orientation, age, disability, or status as a protected veteran, marital status, familial status, physical or mental disability, medical condition, pregnancy, genetic predisposition or carrier status, uniformed service status, political affiliation or any other characteristic protected by applicable national, federal, state, and local law(s).
Please be assured that you will not be subject to any adverse treatment if you choose to disclose the information requested. This information is provided voluntarily. The information obtained will be kept in strict confidence.
For more information, review HP's EEO Policy or read about your rights as an applicant under the law here: " Know Your Rights: Workplace Discrimination is Illegal "
Not included in the source posting: benefits.
Skills
artificial-intelligencemachine-learning
Who can apply
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