DFT Design Engineer

• The Role and Impact

Come join Intel's WCS - Wireless Connectivity Group to shape the future of WiFi/BT experience. The Silicon division of WCS is looking for an experienced DFT engineer to join the design team. As a DFT Design Engineer at Intel, you will play a pivotal role in ensuring the testability and manufacturability of cutting-edge semiconductor products. Your expertise in Design for Test (DFT) will drive quality and efficiency in our product development lifecycle, enabling rapid bring-up and ramp to mass production. By collaborating with cross-functional teams, you will directly impact Intel's ability to deliver high-performance and reliable solutions to our customers, furthering our mission to shape the future of technology.

This is an opportunity to join a team at the forefront of innovation, where your contributions will influence the design and functionality of Intel's most advanced products, ensuring they meet the industry's highest standards in quality, performance, and scalability.

• Key Responsibilities
• Develop logic design, register transfer level (RTL) coding, and simulation for DFT features such as SCAN, MBIST, and BSCAN.
• Provide DFT timing closure support and deliver test content to manufacturing.
• Collaborate in defining architecture and microarchitecture features for blocks, subsystems, and SoCs under DFT design.
• Apply strategies and tools to write and generate RTL and structural code for DFT integration.
• Optimize designs to meet power, performance, area, timing, test coverage, defect per million (DPM), and test time/vector memory reduction goals.
• Review and drive verification plans to ensure architecture and microarchitecture specifications are met.
• Debug and resolve failing RTL tests to ensure feature correctness.
• Integrate DFT blocks into functional IP and SoC, and support SoC customers for high-quality IP block integration.
• Collaborate with post-silicon and manufacturing teams to verify features on silicon, support debug requirements, and document learnings for future improvements.
• Drive high test coverage to meet quality and DPM objectives, and develop high-volume manufacturing content for production on automatic test equipment (ATE).

• Minimum Qualifications
• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• 4+ years of experience wit in DFT engineering.
• Strong knowledge of SCAN ATPG
• Hands-on experience with RTL design, System Verilog, and digital design fundamentals.
• Proficiency in EDA tools and techniques, such as Lint tools and MCO/timing/clock exception handling.
• Expertise in specialized areas such as Scan ATPG and test automation.

• Preferred Qualifications
• Demonstrated problem-solving skills with the ability to address design challenges in complex projects.
• Strong communication and collaboration skills to effectively work with cross-functional teams.
• Experience in driving innovative solutions to improve test coverage, test time efficiency, and overall design quality.
• A commitment to continuous learning and staying at the forefront of DFT advancements.