Senior SoC Chiplet Architect

1. Define the monolithic vs. chiplet decision framework and multi-generation roadmap, incorporating reticle scaling limits, yield economics, modularity, and portfolio reuse strategy
2. Lead architecture studies for 2-die / 3-die / multi-chiplet scaling (compute + I/O/network + memory/accelerators), including partition boundaries, SKU scalability, and future-proof modular upgrades
3. Produce executive-ready architecture options and recommendations for leadership decisions (build/partner/standardize)

1. Drive functional partitioning across chiplets (compute, networking/I/O, accelerators, memory controllers, security/management), balancing PPA, D2D bandwidth/latency, validation complexity, and product flexibility
2. Define scalable system resource models (e.g., memory channels, PCIe lanes, pipeline scaling) and how these scale with chiplet count and topology
3. Specify any required logic / gaskets and integration constraints to enable modular assembly and consistent SW-visible behavior

1. Architect D2D communication for high bandwidth, low latency, and reliability across chiplets; define link budgets and requirements for bandwidth, latency, error handling, and flow control
2. Define inter-chiplet QoS mechanisms (e.g., arbitration, prioritization, isolation) and ensure the architecture supports workload-driven traffic patterns at scale
3. Align D2D choices with industry standardization direction (where applicable) and ensure project-specific needs can be encapsulated cleanly

1. Define coordinated power delivery and power management flows across chiplets (telemetry, quiescence, package states, throttling), including system-level sequencing and corner cases
2. Architect clocking and reset distribution (reference clock delivery, local PLL strategies, reset sequencing, debug/manufacturing hooks) and ensure robust bring-up across all dies
3. Drive the chiplet-aware boot and early firmware architecture (e.g., parallel boot considerations, coordinated reset control) in partnership with FW/platform teams

1. Define cross-chiplet error reporting, containment, and recovery policies, including consistent crashdump, telemetry access, and actionable observability for post-silicon debug
2. Specify debug/trace infrastructure assumptions to ensure chiplet partitioning does not compromise lab efficiency or field diagnosability

1. Lead quantitative trade studies across performance, power, area, cost/yield, and schedule; identify bottlenecks and propose architecture-level mitigations
2. Partner with packaging/manufacturing stakeholders for trade-off comparisons (e.g., explicitly tracking whether packaging overheads are included in a given analysis)

1. Drive alignment across architecture, RTL, DV, FW/SW, packaging, and platform teams; lead reviews, challenge assumptions, and converge on clear architectural decisions
2. Work with other architects and contribute reusable patterns/checklists for chiplet-based SoC infrastructure

:

Batchelor's degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study. You must have 7 + years of experience in the following:

• SoC/system architecture, including end-to-end architecture definition from requirements to silicon execution
• Experience with multi-die / chiplet partitioning and the associated system implications (D2D, boot/reset, cross-domain QoS, debug)
• Run architecture trade-off studies and communicate decisions crisply to senior technical and business stakeholders

:

• Familiarity with industry direction on chiplet interoperability and standardization and/or participation in ecosystem discussions
• Hands-on experience with system bring-up flows and architecture-driven debug/telemetry planning across complex SoCs
• Architecture fundamentals in interconnects/fabrics, memory subsystem behavior, performance modeling, and PPA tradeoffs
• Experience building or consuming cost/yield models for architectural decision-making (including explicitly scoping what cost elements are included)

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 07/31/2026

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