Staff Digital Physical Implementation and Integration Engineer

• Contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits
• Parasitic modeling and assisting in design validation, reticle experiments and required tape-out revisions
• Leading all aspects of and managing the layout process including floor-planning, placement, and routing
• Performing verification processes with modeling and simulation using industry standard simulators
• Contributing to cross group communication to work towards standardization and group success
• Working with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product
• Proactively solicit mentorship from Standards, CAD, modeling, and verification groups to improve the design quality
• Driving innovation into the future Memory generations within a dynamic work environment

• Perform top-level

to derive congestion, timing, and pin-feasibility signals that drive planning decisions.

• Own

: block shaping, abutment, channel/keep-out definition, and power-domain planning.

• Drive

— pin placement, alignment, and count reduction guided by top-level routing.

• Plan and

: budget top-level nets, place repeaters, and manage crossings across partition boundaries.

• Generate

(timing budgets, boundary SDC, ILM/ETM models, physical constraints) directly from the design planning tool and hand them off to block owners.

• Perform top-level assembly: integrate block-related work (LEF/DEF/GDS/ETM/ILM), close top-level timing, DRC, LVS, and EM/IR, and iterate ECOs to convergence.

• Implement full APR flow (init → floorplan → place → CTS → route → ECO → sign-off) on digital blocks; own block-level STA sign-off across corners alongside DRC, LVS, EM/IR, and antenna closure.
• Set up new project and revision environments — collateral (SDC, netlist, LEF, QTM), stdlib migrations, and constraint authoring.
• Debug and correlate synthesis vs. APR vs. STA (PPA regressions, DRV, size_only/don't_touch strategy, scan chain stitching).

• Automate flows in Tcl / SKILL / Python; extend internal make-based flow and contribute to shared analysis tooling and dashboards.
• Partner with STA, DFT, CAD, and custom-layout teams; document methodology and provide mentorship to engineers gaining experience.

of digital physical design with at least one full tapeout owned end-to-end.

• Bachelor’s degree in Computer Engineering or Electrical Engineering

•

block abstractions and ECO fixing.

• Hands-on expertise with

— virtual flat, partitioning, pin optimization, budgeting, assembly.

• Proven experience with

end-to-end — driving a full-chip or large-partition design from planning through assembly and hand-off.

• Strong flat APR expertise with

for multi-mode/multi-corner designs; ability to derive and validate block budgets from top-level planning.

• Fluent in

and one of Python/Perl for flow automation.

• Working proficiency with general-purpose agentic AI applied to engineering work — AI-powered assistants, MCP-based tool integration, and workflow automation. Candidates must be able to use and extend our internal AI toolkit from day one.
• Solid grasp of

, standard cells, RC extraction, EM/IR, and low-power techniques (MV, power gating, retention).

• Linux/Unix, Git or similar VCS, Make-based flows.

• Master’s degree or Ph.D. in Computer Engineering or Electrical Engineering
• Multi-partition SoC or memory top-level integration; experience driving ECOs across a hierarchy of 5+ blocks.

•

design experience; comfort working alongside custom-layout and circuit designers.

• Familiarity with

and their interaction with partitioning.

• Familiarity with

— Cadence Cerebrus / JedAI, Synopsys DSO.ai and copilots, or equivalent.

• Contributions to methodology or CAD tooling (published or internal).

The US base salary range that Micron Technology estimates it could pay for this full-time position is:

$145,000.00 - $246,000.00 a year Additional compensation may include benefits, bonuses and equity. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future.  We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget.  Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave.  Additionally, Micron benefits include a robust paid time-off program and paid holidays.   For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits .

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

To learn about your