Senior Analog Design Engineer

The Hard IP and Test Chip Development team, within Intel's Central Engineering Group, is responsible for delivering industrydefining analog and mixedsignal IP for Intel's Client, Datacenter, AI and Foundry customers. The IO team owns high-speed serial IO and die-to-die interfaces across multiple advanced process nodes. We are seeking an experienced Senior Analog Design Engineer to join our engineering team. The successful candidate will be responsible for designing, developing, and optimizing analog and mixed-signal integrated circuits for various applications. This role requires deep technical expertise in analog circuit design and the ability to lead complex projects from concept to production.

Key Responsibilities

Design and Development

• Design and simulate analog and mixed-signal circuits including amplifiers, data converters, voltage regulators, PLLs, and other analog building blocks.
• Develop circuit architectures and perform detailed transistor-level design.
• Create and optimize layouts working closely with layout engineers.
• Perform circuit analysis, simulation, and verification using industry-standard tools (Cadence, Synopsys, etc.) using approaches that enable automation and take advantage of available AI-supported solutions.

Technical Leadership

• Lead analog design projects from specification to silicon validation.
• Mentor junior engineers and provide technical guidance.
• Collaborate with cross-functional teams including architecture, logic, verification, physical design, layout, post-silicon manufacturing and validation teams, and SOC partners.
• Drive design reviews and ensure adherence to design methodologies.
• Facilitate design development and convergence across global teams designing concurrently in numerous process nodes. You will be expected to work with teams in the US and India to ensure design interoperability and solve problems to deliver designs that meet quality and KPI goals.

Validation and Optimization

• Develop test plans and oversee silicon characterization.
• Debug and resolve design issues during pre and post-silicon phases.
• Optimize designs for performance, power, and area requirements.
• Ensure designs meet specifications and industry standards.

Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field. 6+ years of experience in analog/mixed-signal circuit design for high-speed SerDes or similar applications.

Your experience must include:

• Proven experience in one or more of the following areas: PLL, CDR, CTLE, DFE, ADC, RX AFE, Transmitter (TX), Power Delivery design, IP floor planning, IP top level performance simulation, signal integrity analysis.
• High-speed IO calibration and training algorithms.
• High-speed communication standards such as UCIE and PCIe (Gen5/Gen6/Gen7).
• Core analog design principles, including noise, linearity, matching, and stability.
• Hands-on experience with advanced FinFET CMOS process technologies.
• Analog design and simulation tools such as Cadence Virtuoso/ADE, HSPICE, or equivalent.
• Post-silicon validation, lab measurements, and debug of analog circuits.

• Master's degree in Electrical Engineering, Electronics Engineering, or a related discipline.
• 7+ years of experience in analog design for high-speed SerDes and/or die-to-die applications.
• In-depth understanding of transmitter and receiver design, CDR loops, and equalization techniques.
• Exposure to next-generation high-speed standards such as PCIe 6.0, 800G Ethernet, or JESD.
• Experience with Verilog-A modeling, MATLAB simulations, and automation scripting (e.g., Python, Tcl).
• Strong understanding of signal integrity concepts, channel modeling, and system-level link analysis.
• Background in standard and advanced package technologies.

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 08/17/2026

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.