Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU

• Apply practical AI workflows where they build leverage, including debug assistance, run triage, summarization, documentation, and workflow automation.

• Build and improve high-speed IO integration, build, simulation, and pre-submit qualification flows for large ASIC IP development.

• Improve CI reliability, turnaround time, debuggability, and scalability across distributed compute environments.

• Root-cause complex failures across development, verification, build systems, tools, infrastructure, and compute environments.

• Turn recurring integration or qualification difficulties into durable automation and process improvements.

• Define, publish, and actively use metrics for integration latency, flow health, failure trends, and engineering efficiency.

• Bring metrics into engineering discussions to guide priorities, forecast risk, and optimize the systems we operate.

• Collaborate with ASIC designers, verification engineers, firmware engineers, methodology teams, and infrastructure partners.

• Dive into unfamiliar technical areas, understand how the system works end to end, and drive ambiguous problems to closure.

• BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.

• 5+ years of relevant industry experience.

• Strong understanding of ASIC development workflows, including builds, simulation, regressions, debug, integration, and qualification.

• Experience with verification methodology such as UVM or similar.

• Strong working knowledge of Verilog/SystemVerilog, including RTL development or pre-silicon verification/debug experience.

• Exposure to industry simulation and debug tools such as VCS, Verdi, Xcelium, or similar.

• Strong programming skills in Python, Perl, or another scripting/systems programming language.

• Experience with SystemVerilog and object-oriented verification environments.

• Strong root-cause analysis skills, especially for intermittent or hard-to-isolate infrastructure failures.

• Self-directed execution: ability to take a loosely defined technical problem, investigate across domains, and deliver a working solution.

• Established passion for infrastructure, automation, and driving efficiency gains outside your core RTL or DV tasks.

• Strong curiosity about how complex systems operate and a track record of diving across build, verification, tooling, and infrastructure boundaries to solve problems.

• Practical experience applying AI tools to engineering workflows, including debug automation, summarization, or tool-assisted development.

• Strong engineering habits centered on clear data: defining useful signals, using them in technical conversations, and optimizing systems against them.

• Experience providing ASIC IP for several products, projects, or SoCs simultaneously.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits .

Applications for this job will be accepted at least until August 17, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.