Solution Director

Candidates with minimum

is mandatory

:    Good understanding of ASIC/SoC life cycle

Has participated in multiple ASIC/SoC verification till  tapeout stage

Experience writing ASIC/SoC testplans

1.Experience in ASIC/SoC Testbench definition 2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM)."

1.Expertise & hands-on experience in OVM/UVM methodologies using SV 2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans.

Experience in Gate level simulation & netlist debugging

Experience in regression failure analysis, Functional and Code Coverage closure

Experience in Utilizing scripting languages like Perl/Shell scripting to automate regression tests and parse large simulation log files. Experience in Collaborating closely with the hardware design team to analyze, document, and resolve bug reports efficiently. Experience in Document test plans, micro-architecture specifications, and verification results for team reviews

Experience to lead the micro-architecture and full-chip verification of our next-generation semiconductor products End-to-end ownership of complex IPs and subsystems, from defining functional specifications to managing final tape-out sign-off. You will architect robust, scalable UVM environments, solve critical architectural bottlenecks, and mentor a team of engineers to ensure first-pass silicon success

Develop complex verification components, including bus functional models (BFMs), monitors, predictors, and highly parameterized scoreboards. Oversee and resolve deep technical issues in Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), linting, and formal verification. Direct the deployment of advanced verification techniques such as Formal Verification, Hardware Emulation (e.g., Palladium, Zebu), and Power-Aware (UPF/CPF) simulations.

Act as the primary technical point of contact, interfacing with System Architects, Backend/Physical Design teams, and Post-Silicon Validation teams. Provide technical mentorship, code reviews, and career guidance to junior and mid-level design and verification engineers. Establish, standardize, and continuously improve engineering methodologies, automation scripts, and best practices across the organization.

Experience in defining micro-architecture specifications for high-performance, low-power digital design blocks and subsystems. Architect advanced, scalable, and reusable constrained-random verification environments from scratch at the SoC and subsystem levels using SystemVerilog and UVM. Lead the definition of comprehensive design verification (DV) plans, test strategies, and coverage metrics for highly complex SoC features. Drive critical technical reviews including design specifications, test plans, RTL code quality, and verification completeness.

Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical Engineering (EE), VLSI Design, or a closely related field"

Proven industry experience in ASIC/SoC design and verification with multiple successful tape-outs.

Mastery of SystemVerilog, Verilog, and UVM (Universal Verification Methodology).

Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts.

Strong understanding of CPU/GPU architectures, cache coherency, and memory controllers (e.g., DDR4/DDR5, HBM) is highly desirable."

Expert proficiency with industry-leading EDA simulators, debuggers (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verd), and emulation platforms.

Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C,PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE)."

Advanced capability in Python, Tcl, or Perl to create custom automation infrastructure for regressions and metrics tracking.

Ability to foresee technical risks weeks or months in advance and proactively implement mitigation strategies.

Strong leadership and communication skills to guide cross-functional teams and align stakeholders on technical directions.